Publications

You can also find my articles on my Google Scholar profile.

Publications

Books

  1. P. Santikellur and R. S. Chakraborty, “Deep Learning for Computational Problems in Hardware Security: Modeling Attacks on Strong Physically Unclonable Function Circuits”, Vol. 1052. Springer Nature, 2022. Link

  2. S. Roy, P. Santikellur and R. S. Chakraborty, “Machine Learning and Deep Learning Meets Computer Networks”, Springer (forthcoming)

Journal Papers

  1. P. Santikellur, M. Buddhanoy, S. Sakib, B. Ray and R.S Chakraborty, “A Shared Page-Aware Machine Learning Assisted Method for Predicting and Improving Multi-Level Cell NAND Flash Memory Life Expectancy”, Microelectronics Reliability, 140, p.114867. Link

  2. P. Santikellur and R. S. Chakraborty, “Correlation Integral based Intrinsic Dimension: a Deep Learning Assisted Empirical Metric to Estimate the Robustness of Physically Unclonable Functions to Modeling Attacks”, in IEEE Transactions on Computer-Aided Design of IntegratedCircuits and Systems, vol. 41, no. 10, pp. 3216-3227, Oct. 2022. Link

  3. S. Chattaopadhyay, P. Santikellur, R. S. Chakraborty, J. Mathew and M. Ottavi, “A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability”, in ACM Transactions on Design Automation of Electronic Systems, 26, 6, Article 41 (November 2021), pp.1-2. Link

  4. P. Santikellur and R. S. Chakraborty, “A Computationally Efficient Tensor Regression Network based Modeling Attack on XOR Arbiter PUF and its Variants” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems., vol. 40, no. 6, pp. 1197-1206, June 2021. Link

  5. V. Govindan, R. S. Chakraborty, P. Santikellur., A.K Chaudhary, “A Hardware Trojan Attack on FPGA based Cryptographic Key Generation: Impact and Detection”, Journal of Hardware and Systems Security (Springer), vol. 2, no. 3, pp. 225-239, Sep. 2018. Link

Book Chapters

  1. P. Santikellur, R. S. Chakraborty, and J. Mathew, “Hardware Security in the Context of Internet of Things: Challenges and Opportunities.” Internet of Things and Secure Smart Environments: Successes and Pitfalls,2020, p.64. Link
  2. P. Santikellur, R. S. Chakraborty, S. Bhunia, (2022). “Hardware IP Protection Using Register Transfer Level Locking and Obfuscation of Controland Data Flow.” Behavioral Synthesisfor Hardware Security. Springer, Cham. Link

Conference Papers

  1. P. Santikellur, R. Mukherjee, and R. S. Chakraborty. “APUF-BNN: AnAutomated Framework for Efficient Combinational Logic Based Implementation of Arbiter PUF through Binarized Neural Network”. In Proceedings of the 2021 on Great Lakes Symposium on VLSI (GLSVLSI ’21). Association for Computing Machinery, New York, NY, USA, 89–94. (Best Paper Nominated) Link
  2. P. Santikellur, Lakshya, S. R. Prakash and R. S. Chakraborty, “A Computationally Efficient Tensor Regression Network based Modeling Attack on XOR Arbiter PUF”, IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 2019, pp. 1-6. Link