Publications
Book
P. Santikellur and R. S. Chakraborty, “Deep Learning for ComputationalProblems in Hardware Security: Modeling Attacks on Strong Physically Unclonable Function Circuits”, Vol. 1052. Springer Nature, 2022. doi: https://doi.org/10.1007/978-981-19-4017-0
Journal Papers
P. Santikellur, M. Buddhanoy, S. Sakib, B. Ray and R.S Chakraborty, "A Shared Page-Aware Machine Learning Assisted Method for Predicting and Improving Multi-Level Cell NAND Flash Memory Life Expectancy", Microelectronics Reliability, 140, p.114867.
Link: https://doi.org/10.1016/j.microrel.2022.114867
P. Santikellur and R. S. Chakraborty, "Correlation Integral based Intrinsic Dimension: a Deep Learning Assisted Empirical Metric to Estimate the Robustness of Physically Unclonable Functions to Modeling Attacks," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 10, pp. 3216-3227, Oct. 2022
Link: https://doi.org/10.1109/TCAD.2021.3129112
S. Chattaopadhyay, P. Santikellur, R. S. Chakraborty, J. Mathew and M. Ottavi,”A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability”,in ACM Transactions on Design Automation of Electronic Systems, 26, 6, Article 41 (November 2021), pp. 1-24.
Link: https://doi.org/10.1145/3460004
P. Santikellur and R. S. Chakraborty, ”A Computationally Efficient Tensor Regression Network based Modeling Attack on XOR Arbiter PUF and its Variants”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems., vol. 40, no. 6, pp. 1197-1206, June 2021.
Link: https://doi.org/10.1109/TCAD.2020.3032624.
V. Govindan, R. S. Chakraborty, P. Santikellur. , A.K Chaudhary, ”A Hardware Trojan Attack on FPGA based Cryptographic Key Generation: Impact and Detection”, Journal of Hardware and Systems Security (Springer), vol. 2, no. 3,pp. 225-239, Sep. 2018.
Link: https://doi.org/10.1007/s41635-018-0042-5
Conference Papers
P. Santikellur, R. Mukherjee and R. S. Chakraborty, “APUF-BNN: An Automated Framework for Efficient Combinational Logic Based Implementation of Arbiter PUF through Binarized Neural Network”, In Proceedings of the 2021 on Great Lakes Symposium on VLSI (GLSVLSI '21). Association for Computing Machinery, New York, NY, USA, 89–94. (Best Paper Nominated)
P. Santikellur, Lakshya, S. R. Prakash and R. S. Chakraborty, ”A Computationally Efficient Tensor Regression Network based Modeling Attack onXOR Arbiter PUF”,IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Xi’an, P.R. China, 2019.
V. S. Balijabudda, D. Thapar, P. Santikellur, R. S. Chakraborty and I.Chakrabarti, ”Design of a Chaotic Oscillator based Model Building Attack Resistant Arbiter PUF”,IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Xi’an, China, 2019.
U.Chatterjee, P. Santikellur, R. Sadhukhan, V. Govindan, D. Mukhopadhyayand R. S. Chakraborty, “United We Stand: A Threshold Signature Scheme forIdentifying Outliers in PLCs (poster with 2 page short-paper)”, Late Breaking Results (LBR) track of IEEE/ACM Design Automation Conference (DAC), LasVegas, Nevada, USA, 2019.
Book Chapter
P. Santikellur, R. S. Chakraborty, and J. Mathew, ”Hardware Securityin the Context of Internet of Things: Challenges and Opportunities.”Internet of Things and Secure Smart Environments: Successes and Pitfalls,p.299.
P. Santikellur,R. S. Chakraborty, S. Bhunia, (2022). Hardware IP Protection Using Register Transfer Level Locking and Obfuscation of Control and Data Flow. In: Katkoori, S., Islam, S.A. (eds) Behavioral Synthesis for Hardware Security. Springer, Cham.